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FDH038AN08A1
February 2003
FDH038AN08A1
N-Channel PowerTrench(R) MOSFET 75V, 80A, 3.8m
Features
* r DS(ON) = 3.5m (Typ.), V GS = 10V, ID = 80A * Qg(tot) = 125nC (Typ.), VGS = 10V * Internal Gate Resistor, Rg = 20 (Typ.) * Low Miller Charge * Low QRR Body Diode * UIS Capability (Single Pulse and Repetitive Pulse) * Qualified to AEC Q101
Formerly developmental type 82690 SOURCE DRAIN GATE G D
Applications
* 42V Automotive Load Control * Starter / Alternator Systems * Electronic Power Steering Systems * Electronic Valve Train Systems * DC-DC converters and Off-line UPS * Distributed Power Architectures and VRMs * Primary Switch for 24V and 48V systems
TO-247
S
MOSFET Maximum Ratings TC = 25C unless otherwise noted
Symbol VDSS VGS Parameter Drain to Source Voltage Gate to Source Voltage Drain Current ID Continuous (TC < 158oC, VGS = 10V) Continuous (TA = 25oC, VGS = 10V, with RJA = 30oC/W) Pulsed EAS PD TJ, TSTG Single Pulse Avalanche Energy (Note 1) Power dissipation Derate above 25oC Operating and Storage Temperature 80 22 Figure 4 1.17 450 3.0 -55 to 175 A A A J W W/oC
oC
Ratings 75 20
Units V V
Thermal Characteristics
RJC RJA Thermal Resistance Junction to Case TO-247 Thermal Resistance Junction to Ambient TO-247 0.33 30
oC/W oC/W
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/ Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html. All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
(c)2003 Fairchild Semiconductor Corporation
FDH038AN08A1 Rev A
FDH038AN08A1
Package Marking and Ordering Information
Device Marking FDH038AN08A1 Device FDH038AN08A1 Package TO-247 Reel Size Tube Tape Width N/A Quantity 30 units
Electrical Characteristics TC = 25C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BVDSS IDSS IGSS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 250A, VGS = 0V V DS = 60V VGS = 0V VGS = 20V TC = 150oC 75 1 250 100 V A nA
On Characteristics
VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250A ID = 80A, VGS = 10V rDS(ON) Drain to Source On Resistance ID = 40A, VGS = 6V ID = 80A, VGS = 10V, TJ = 175oC 2 4 V 0.0035 0.0038 0.0047 0.0071 0.0074 0.008
Dynamic Characteristics
CISS COSS CRSS Qg(TOT) Qg(TH) Qgs Qgs2 Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge at 10V Threshold Gate Charge Gate to Source Gate Charge Gate Charge Threshold to Plateau Gate to Drain "Miller" Charge V DS = 25V, VGS = 0V, f = 1MHz VGS = 0V to 10V VGS = 0V to 2V VDD = 40V ID = 80A Ig = 1.0mA 8665 1320 340 125 17 57 42 30 160 22 pF pF pF nC nC nC nC nC
Switching Characteristics (VGS = 10V)
tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time V DD = 40V, ID = 80A VGS = 10V, RGS = 2.4 88 141 232 126 345 530 ns ns ns ns ns ns
Drain-Source Diode Characteristics
VSD trr QRR Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge ISD = 80A ISD = 40A ISD = 75A, dISD/dt = 100A/s ISD = 75A, dISD/dt = 100A/s 1.25 1.0 50 65 V V ns nC
Notes: 1: Starting TJ = 25C, L = 0.65mH, IAS = 60A.
(c)2003 Fairchild Semiconductor Corporation
FDH038AN08A1 Rev. A
FDH038AN08A1
Typical Characteristics TC = 25C unless otherwise noted
1.2 280 240 ID, DRAIN CURRENT (A) 200 160 120 80 40 VGS = 10V 0 0 25 50 75 100 125 150 175 TC , CASE TEMPERATURE (oC) 25 50 75 100 125 TC, CASE TEMPERATURE (oC) 150 175 CURRENT LIMITED BY PACKAGE
POWER DISSIPATION MULTIPLIER
1.0
0.8
0.6
0.4
0.2
0
Figure 1. Normalized Power Dissipation vs Ambient Temperature
2 1 ZJC, NORMALIZED THERMAL IMPEDANCE DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01
Figure 2. Maximum Continuous Drain Current vs Case Temperature
RJA=30oC/W
PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10 -3 10-2 10-1 t , RECTANGULAR PULSE DURATION (s) 100 101
SINGLE PULSE 0.01 10-5 10-4
Figure 3. Normalized Maximum Transient Thermal Impedance
3000 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION TC = 25 oC FOR TEMPERATURES ABOVE 25o C DERATE PEAK CURRENT AS FOLLOWS: I = I25 VGS = 10V 175 - TC 150
IDM, PEAK CURRENT (A)
1000
100
50 10-5 10-4 10-3 10-2 t, PULSE WIDTH (s) 10-1 100 101
Figure 4. Peak Current Capability
(c)2003 Fairchild Semiconductor Corporation
FDH038AN08A1 Rev. A
FDH038AN08A1
Typical Characteristics TC = 25C unless otherwise noted
2000 1000 10s 100s ID, DRAIN CURRENT (A) 100 IAS, AVALANCHE CURRENT (A) 500 If R = 0 tAV = (L)(I AS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] STARTING TJ = 25oC
100
1ms 10ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) SINGLE PULSE TJ = MAX RATED TC = 25oC 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100
10
10 STARTING TJ = 150oC
DC
1
1 0.01 0.1 1 10 tAV, TIME IN AVALANCHE (ms) 100
0.1 0.1
Figure 5. Forward Bias Safe Operating Area
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching Capability
160
160 PULSE DURATION = 80ms DUTY CYCLE = 0.5% MAX VDD = 15V ID , DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 120 TJ = 80 TJ = 25oC 40 TJ = -55 oC 175oC
VGS = 10V 120 VGS = 6V 80
VGS = 7V
VGS = 5V
40 TC = 25oC PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VGS , GATE TO SOURCE VOLTAGE (V)
0 0 0.5 1.0 VDS , DRAIN TO SOURCE VOLTAGE (V) 1.5
Figure 7. Transfer Characteristics
6 NORMALIZED DRAIN TO SOURCE ON RESISTANCE
Figure 8. Saturation Characteristics
2.5
DRAIN TO SOURCE ON RESISTANCE(m)
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
VGS = 6V 5
2.0
4 VGS = 10V
1.5
3 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 2 0 20 40 ID, DRAIN CURRENT (A) 60 80
1.0
VGS = 10V, ID = 80A 0.5 -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) 160 200
Figure 9. Drain to Source On Resistance vs Drain Current
Figure 10. Normalized Drain to Source On Resistance vs Junction Temperature
(c)2003 Fairchild Semiconductor Corporation
FDH038AN08A1 Rev. A
FDH038AN08A1
Typical Characteristics TC = 25C unless otherwise noted
1.4 VGS = VDS, ID = 250A 1.2 NORMALIZED GATE THRESHOLD VOLTAGE NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.2 ID = 250A
1.0
1.1
0.8
0.6
1.0
0.4
0.2 -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (o C) 160 200
0.9 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) 200
Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature
20000 10000 C, CAPACITANCE (pF)
Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature
10 VDD = 40V VGS , GATE TO SOURCE VOLTAGE (V) 8
CISS = CGS + C GD
COSS CDS + CGD
6
1000
CRSS = CGD
4 WAVEFORMS IN DESCENDING ORDER: ID = 80A ID = 40A 0 25 50 75 Qg, GATE CHARGE (nC) 100 125
2
VGS = 0V, f = 1MHz 100 0.1 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 75
0
Figure 13. Capacitance vs Drain to Source Voltage
Figure 14. Gate Charge Waveforms for Constant Gate Currents
(c)2003 Fairchild Semiconductor Corporation
FDH038AN08A1 Rev. A
FDH038AN08A1
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP 0V RG IAS VDD VDD tP VDS
+
IAS 0.01 0 tAV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
VDS VDD L VGS VDS VGS
+
Qg(TOT)
VGS = 10V
VDD DUT Ig(REF) VGS = 2V 0
Qgs2
Qg(TH) Qgs Ig(REF) 0 Qgd
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VDS
tON td(ON) RL VDS
+
tOFF td(OFF) tr tf 90%
90%
VGS
VDD DUT 0
10%
10%
RGS VGS VGS 0 10% 50% PULSE WIDTH
90% 50%
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
(c)2003 Fairchild Semiconductor Corporation
FDH038AN08A1 Rev. A
FDH038AN08A1
PSPICE Electrical Model
.SUBCKT FDH038AN08A1 2 1 3 ; CA 12 8 1.0e-9 Cb 15 14 3.1e-9 Cin 6 8 8.22e-9 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD Ebreak 11 7 17 18 84.9 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 Lgate 1 9 4.81e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 4.63e-9 RLgate 1 9 48.1 RLdrain 2 5 10 RLsource 3 7 46.3 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 2.0e-4 Rgate 9 20 20 RSLC1 5 51 RSLCMOD 1.0e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 2.6e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*300),10))} .MODEL DbodyMOD D (IS=2.4E-11 N=1.02 RS=1.65e-3 TRS1=3.2e-3 TRS2=2.0e-7 + CJO=6.0e-9 M=5.6e-1 TT=2.38e-8 XTI=3.9) .MODEL DbreakMOD D (RS=1.5e-1 TRS1=1.0e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=1.5e-9 IS=1.0e-30 N=10 M=0.47) .MODEL MmedMOD NMOS (VTO=3.2 KP=1.5 IS=1.0e-30 N=10 TOX=1 L=1u W=1u RG=20) .MODEL MstroMOD NMOS (VTO=3.95 KP=235 IS=1.0e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=2.73 KP=0.02 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=200 RS=.01) .MODEL RbreakMOD RES (TC1=1.05e-3 TC2=-9.0e-7) .MODEL RdrainMOD RES (TC1=1.8e-2 TC2=2.2e-4) .MODEL RSLCMOD RES (TC1=2.0e-3 TC2=1.0e-5) .MODEL RsourceMOD RES (TC1=5.0e-3 TC2=1.0e-6) .MODEL RvthresMOD RES (TC1=-4.2e-3 TC2=-1.8e-5) .MODEL RvtempMOD RES (TC1=-4.5e-3 TC2=2.0e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-1.5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=0.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.5 VOFF=-0.5) .ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. FrankWheatley.
GATE 1 RLGATE CIN
rev January 2003
LDRAIN DPLCAP 10 RSLC1 51 ESLC 50 RDRAIN EVTHRES + 19 8 6 MSTRO LSOURCE 8 RSOURCE S1A 12 13 8 S1B CA 13 + EGS 6 8 EDS S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT 15 17 RBREAK 18 RVTEMP 19 VBAT + 22 7 RLSOURCE SOURCE 3 21 16 RLDRAIN DBREAK 11 + 17 EBREAK 18 MWEAK MMED 5 DRAIN 2
RSLC2
5 51 ESG + LGATE EVTEMP RGATE + 18 22 9 20 6 8 -
(c)2003 Fairchild Semiconductor Corporation
+
DBODY
FDH038AN08A1 Rev. A
FDH038AN08A1
SABER Electrical Model
REV January 2003 template FDH038AN08A1 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=2.4e-11,nl=1.02,rs=1.65e-3,trs1=3.2e-3,trs2=2.0e-7,cjo=6.0e-9,m=5.6e-1,tt=2.38e-8,xti=3.9) dp..model dbreakmod = (rs=1.5e-1,trs1=1.0e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=1.5e-9,isl=10e-30,nl=10,m=0.47) m..model mmedmod = (type=_n,vto=3.2,kp=1.5,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=3.95,kp=235,is=1.0e-30, tox=1) m..model mweakmod = (type=_n,vto=2.73,kp=0.02,is=1.0e-30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-1.5) sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-1.5,voff=-4) sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.5,voff=0.5) sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.5,voff=-0.5) LDRAIN c.ca n12 n8 = 1.0e-9 DPLCAP 5 c.cb n15 n14 = 3.1e-9 10 c.cin n6 n8 = 8.22e-9 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 84.9 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 GATE spe.evtemp n20 n6 n18 n22 = 1 1 i.it n8 n17 = 1 l.lgate n1 n9 = 4.81e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 4.63e-9 res.rlgate n1 n9 = 48.1 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 46.3
CA 12 S1B 13 + EGS 6 8 EDS ESG + LGATE EVTEMP RGATE + 18 22 9 20 6 MSTRO CIN 8 6 8 EVTHRES + 19 8 RSLC1 51 RSLC2 ISCL 50 RDRAIN 21 16 MWEAK MMED EBREAK + 17 18 DBREAK 11 DBODY
DRAIN 2
RLDRAIN
RLGATE
LSOURCE 7 RLSOURCE
SOURCE 3
RSOURCE S1A 13 8 S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT VBAT + 22 15 17 RBREAK 18 RVTEMP 19
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=1.05e-3,tc2=-9.0e-7 res.rdrain n50 n16 = 2.0e-4, tc1=1.8e-2,tc2=2.2e-4 res.rgate n9 n20 = 20 res.rslc1 n5 n51 = 1e-6, tc1=2.0e-3,tc2=1.0e-5 res.rslc2 n5 n50 = 1.0e3 res.rsource n8 n7 = 2.6e-3, tc1=5.0e-3,tc2=1.0e-6 res.rvthres n22 n8 = 1, tc1=-4.2e-3,tc2=-1.8e-5 res.rvtemp n18 n19 = 1, tc1=-4.5e-3,tc2=2.0e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/300))** 10)) } }
(c)2003 Fairchild Semiconductor Corporation
FDH038AN08A1 Rev. A
FDH038AN08A1
SPICE Thermal Model
REV 23 January 2003 FDH038AN08A1T CTHERM1 TH 6 5.5e-3 CTHERM2 6 5 6.0e-3 CTHERM3 5 4 7.4e-3 CTHERM4 4 3 7.65e-3 CTHERM5 3 2 5.85e-2 CTHERM6 2 TL 6.0e-1 RTHERM1 TH 6 9.0e-3 RTHERM2 6 5 2.08e-2 RTHERM3 5 4 2.28e-2 RTHERM4 4 3 7.0e-2 RTHERM5 3 2 7.5e-2 RTHERM6 2 TL 8.5e-2
th
JUNCTION
RTHERM1
CTHERM1
6
RTHERM2
CTHERM2
5
SABER Thermal Model
SABER thermal model FDH038AN08A1T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =5.5e-3 ctherm.ctherm2 6 5 =6.0e-3 ctherm.ctherm3 5 4 =7.4e-3 ctherm.ctherm4 4 3 =7.65e-3 ctherm.ctherm5 3 2 =5.85e-2 ctherm.ctherm6 2 tl =6.0e-1 rtherm.rtherm1 th 6 =9.0e-3 rtherm.rtherm2 6 5 =2.08e-2 rtherm.rtherm3 5 4 =2.28e-2 rtherm.rtherm4 4 3 =7.0e-2 rtherm.rtherm5 3 2 =7.5e-2 rtherm.rtherm6 2 tl =8.5e-2 }
RTHERM3 CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
CASE
(c)2003 Fairchild Semiconductor Corporation
FDH038AN08A1 Rev. A
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACExTM FACTTM ActiveArrayTM FACT Quiet SeriesTM BottomlessTM FAST(R) CoolFETTM FASTrTM CROSSVOLTTM FRFETTM DOMETM GlobalOptoisolatorTM EcoSPARKTM GTOTM E2CMOSTM HiSeCTM I2CTM EnSignaTM Across the board. Around the world.TM The Power FranchiseTM Programmable Active DroopTM DISCLAIMER
ImpliedDisconnectTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM MSXTM MSXProTM OCXTM OCXProTM OPTOLOGIC(R) OPTOPLANARTM
PACMANTM POPTM Power247TM PowerTrench(R) QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM SILENT SWITCHER(R) SMART STARTTM
SPMTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogic(R) TruTranslationTM UHCTM UltraFET(R) VCXTM
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Preliminary
No Identification Needed
Full Production
Obsolete
Not In Production
Rev. I2

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